HD64F3687HV Datasheet, PDF (280/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
5. Contention between GR Read and Input Capture: If an input capture signal is generated in the
T₁ state of a GR read cycle, the data that is read will be transferred before input capture
transfer. Figure 13.56 shows the timing in this case.
GR read cycle
T1
T2
φ
GR address
Internal read
signal
Input capture
signal
GR
X
M
Internal data
bus
X
Figure 13.56 Contention between GR Read and Input Capture
Rev.5.00 Nov. 02, 2005 Page 246 of 500
REJ09B0027-0500