HD64F3687HV Datasheet, PDF (256/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
Complementary PWM mode
Stop counter operation
[1]
Initialize output pin
[2]
Select counter clock
[3]
Set complementary
[4]
PWM mode
Initialize output pin
[5]
Set TCNT
[6]
Set GR
[7]
Enable waveform output [8]
Start counter operation
[9]
[1] Clear bits STR0 and STR1 in TSTR to 0,
and stop the counter operation of
TCNT_0. Stop TCNT_0 and TCNT_1 and
set complementary PWM mode.
[2] Write H'00 to TOCR.
[3] Use bits TPSC2 to TPSC0 in TCR to
select the same counter clock for channels
0 and 1. When an external clock is
selected, select the edge of the external
clock by bits CKEG1 and CKEG0 in TCR.
Do not use bits CCLR1 and CCLR0 in
TCR to clear the counter.
[4] Use bits CMD1 and CMD0 in TFCR to set
complementary PWM mode. FTIOB0 to
FTIOD0 and FTIOA1 to FTIOD1
automatically become PWM output pins.
[5] Set H'00 to TOCR.
[6] TCNT_1 must be H'0000. Set a non-
overlapped period to TCNT_0.
[7] GRA_0 is a cycle register. Set the cycle to
GRA_0. Set the timing to change the
PWM output waveform to GRB_0, GRA_1,
and GRB_1. Note that the timing must be
set within the range of compare match
carried out for TCNT_0 and TCNT_1.
For GR settings, see 3. Setting GR Value
in Complementary PWM Mode in section
13.4.7.
[8] Use TOER to enable or disable the timer
output.
[9] Set the STR0 and STR1 bits in TSTR to 1
to start the count operation.
<Complementary PWM mode>
Note: To re-enter complementary PWM mode, first, enter a mode other than the complementary
PWM mode. After that, repeat the setting procedures from step [1].
For settings of waveform outputs with a duty cycle of 0% and 100%, see the settings shown
in 2. Examples of Complementary PWM Mode Operation and 3. Setting GR Value in
Complementary PWM Mode in section 13.4.7.
Figure 13.29 Example of Complementar y PWM Mode Setting Procedure
Rev.5.00 Nov. 02, 2005 Page 222 of 500
REJ09B0027-0500