HD64F3687HV Datasheet, PDF (275/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
2. IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag
is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure
13.49 shows the timing.
φ
Input capture
signal
IMF
TCNT
N
GR
N
ITMZ
Figure 13.49 IMF Flag Set Timing at Input Capture
3. Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows.
Figure 13.50 shows the timing.
φ
TCNT
Overflow
signal
OVF
ITMZ
H'FFFF
H'0000
Figure 13.50 OVF Flag Set Timing
Rev.5.00 Nov. 02, 2005 Page 241 of 500
REJ09B0027-0500