HD64F3687HV Datasheet, PDF (243/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
2. Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR. Figure 13.18 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least two system clock (φ) cycles.
φ
Input capture input
Input capture signal
TCNT
GR
N
N
Figure 13.18 Input Capture Signal Timing
Rev.5.00 Nov. 02, 2005 Page 209 of 500
REJ09B0027-0500