HD64F3687HV Datasheet, PDF (276/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
13.5.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 13.51 shows the
timing in this case.
φ
Address
WTSR
(internal write signal)
TSR address
IMF, OVF
ITMZ
Figure 13.51 Status Flag Clearing Timing
13.6 Usage Notes
1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated
in the T₂ state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not
performed. Figure 13.52 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
WTCNT
(internal write signal)
Counter clear signal
TCNT
N
H'0000
Clearing has priority.
Figure 13.52 Contention between TCNT Write and Clear Operations
Rev.5.00 Nov. 02, 2005 Page 242 of 500
REJ09B0027-0500