HD64F3687HV Datasheet, PDF (19/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

16.8.4 Receive Data Sampling Timing and Reception
Margin in Asynchronous Mode ............................................................................ 301
Section 17 I²C Bus Interface 2 (IIC2) ................................................................303
17.1 Features.............................................................................................................................. 303
17.2 Input/Output Pins ............................................................................................................... 305
17.3 Register Descriptions ......................................................................................................... 305
17.3.1 I²C Bus Control Register 1 (ICCR1)..................................................................... 306
17.3.2 I²C Bus Control Register 2 (ICCR2)..................................................................... 308
17.3.3 I²C Bus Mode Register (ICMR)............................................................................ 309
17.3.4 I²C Bus Interrupt Enable Register (ICIER) ........................................................... 311
17.3.5 I²C Bus Status Register (ICSR)............................................................................. 313
17.3.6 Slave Address Register (SAR).............................................................................. 316
17.3.7 I²C Bus Transmit Data Register (ICDRT)............................................................. 317
17.3.8 I²C Bus Receive Data Register (ICDRR).............................................................. 317
17.3.9 I²C Bus Shift Register (ICDRS)............................................................................ 317
17.4 Operation ........................................................................................................................... 318
17.4.1 I²C Bus Format...................................................................................................... 318
17.4.2 Master Transmit Operation ................................................................................... 319
17.4.3 Master Receive Operation..................................................................................... 321
17.4.4 Slave Transmit Operation ..................................................................................... 323
17.4.5 Slave Receive Operation....................................................................................... 325
17.4.6 Clocked Synchronous Serial Format..................................................................... 327
17.4.7 Noise Canceler...................................................................................................... 329
17.4.8 Example of Use..................................................................................................... 330
17.5 Interrupt Request................................................................................................................ 334
17.6 Bit Synchronous Circuit..................................................................................................... 335
17.7 Usage Notes ....................................................................................................................... 336
17.7.1 Issue (Retransmission) of Start/Stop Conditions .................................................. 336
17.7.2 WAIT Setting in I²C Bus Mode Register (ICMR) ................................................ 336
Section 18 A/D Converter..................................................................................337
18.1 Features.............................................................................................................................. 337
18.2 Input/Output Pins ............................................................................................................... 339
18.3 Register Descriptions ......................................................................................................... 340
18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 340
18.3.2 A/D Control/Status Register (ADCSR) ................................................................ 341
18.3.3 A/D Control Register (ADCR) ............................................................................. 342
18.4 Operation ........................................................................................................................... 343
18.4.1 Single Mode.......................................................................................................... 343
Rev.5.00 Nov. 02, 2005 Page xvii of xxxii