HD64F3687HV Datasheet, PDF (234/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
Figure 13.8 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
STR0,
STR1
Time
OVF
Figure 13.8 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The GR registers for setting the period are designated
as output compare registers, and counter clearing by compare match is selected by means of bits
CCLR1 and CCLR0 in TCR. After the settings have been made, TCNT starts an increment
operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count
value matches the value in GR, the IMFA, IMFB, IMFC, or IMFD flag in TSR is set to 1 and
TCNT is cleared to H'0000.
If the value of the corresponding IMIEA, IMIEB, IMIEC, or IMIED bit in TIER is 1 at this point,
the timer Z requests an interrupt. After a compare match, TCNT starts an increment operation
again from H'0000.
Figure 13.9 illustrates periodic counter operation.
Rev.5.00 Nov. 02, 2005 Page 200 of 500
REJ09B0027-0500