HD64F3687HV Datasheet, PDF (204/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 12 Timer V
12.5 Timer V Application Examples
12.5.1 Pulse Output with Arbitrary Duty Cycle
Figure 12.9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORA.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
4. With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
TCNTV value
H'FF
TCORA
TCORB
H'00
TMOV
Counter cleared
Time
Figure 12.9 Pulse Output Example
Rev.5.00 Nov. 02, 2005 Page 170 of 500
REJ09B0027-0500