HD64F3687HV Datasheet, PDF (279/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
4. Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in
the T₂ state of a TCNT write cycle, TCNT write has priority without an increment operation.
At this time, the OVF flag is set to 1. Figure 13.55 shows the timing in this case.
φ
WTCNT
(internal write signal)
TCNT write cycle
T1
T2
TCNT address
TCNT input clock
Overflow signal
TCNT
OVF
H'FFFF
M
TCNT write data
Figure 13.55 Contention between TCNT Write and Overflow
Rev.5.00 Nov. 02, 2005 Page 245 of 500
REJ09B0027-0500