HD64F3687HV Datasheet, PDF (26/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Figure 13.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) ...... 219
Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) ...... 220
Figure 13.29 Example of Complementar y PWM Mode Setting Procedure............................... 222
Figure 13.30 Canceling Procedure of Complementary PWM Mode.......................................... 223
Figure 13.31 Example of Complementary PWM Mode Operation (1) ...................................... 224
Figure 13.32 (1) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 = 0) (2) ................................................................ 225
Figure 13.32 (2) Example of Complementary PWM Mode Operation
(TPSC2 = TPSC1 = TPSC0 ≠ 0) (3) ................................................................ 226
Figure 13.33 Timing of Overshooting ........................................................................................ 227
Figure 13.34 Timing of Undershooting ...................................................................................... 227
Figure 13.35 Compare Match Buffer Operation......................................................................... 230
Figure 13.36 Input Capture Buffer Operation............................................................................. 231
Figure 13.37 Example of Buffer Operation Setting Procedure................................................... 231
Figure 13.38 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register) ................................................. 232
Figure 13.39 Example of Compare Match Timing for Buffer Operation ................................... 233
Figure 13.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register) ...................................................... 234
Figure 13.41 Input Capture Timing of Buffer Operation............................................................ 235
Figure 13.42 Buffer Operation (3) (Buffer Operation in Complementary
PWM Mode CMD1 = CMD0 = 1) ........................................................................ 236
Figure 13.43 Buffer Operation (4) (Buffer Operation in
Complementary PWM Mode CMD1 = CMD0 = 1).............................................. 237
Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER .................. 238
Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger.................... 238
Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ................... 239
Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR................... 239
Figure 13.48 IMF Flag Set Timing when Compare Match Occurs ............................................ 240
Figure 13.49 IMF Flag Set Timing at Input Capture .................................................................. 241
Figure 13.50 OVF Flag Set Timing ............................................................................................ 241
Figure 13.51 Status Flag Clearing Timing.................................................................................. 242
Figure 13.52 Contention between TCNT Write and Clear Operations....................................... 242
Figure 13.53 Contention between TCNT Write and Increment Operations ............................... 243
Figure 13.54 Contention between GR Write and Compare Match............................................. 244
Figure 13.55 Contention between TCNT Write and Overflow................................................... 245
Figure 13.56 Contention between GR Read and Input Capture.................................................. 246
Figure 13.57 Contention between Count Clearing and Increment
Operations by Input Capture ................................................................................ 247
Figure 13.58 Contention between GR Write and Input Capture................................................. 248
Rev.5.00 Nov. 02, 2005 Page xxiv of xxxii