HD64F3687HV Datasheet, PDF (360/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 17 I²C Bus Interface 2 (IIC2)
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
4. The last byte data is read by reading ICDRR.
SCL
(Master output)
9
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
A
RDRF
1
2
3
4
5
6
7
8
9
1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
A
ICDRS
Data 1
Data 2
ICDRR
User
processing
Data 1
[2] Read ICDRR (dummy read)
[2] Read ICDRR
Figure 17.11 Slave Receive Mode Operation Timing (1)
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
RDRF
9
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
A
A
ICDRS
Data 1
Data 2
ICDRR
User
processing
Data 1
[3] Set ACKBT [3] Read ICDRR [4] Read ICDRR
Figure 17.12 Slave Receive Mode Operation Timing (2)
Rev.5.00 Nov. 02, 2005 Page 326 of 500
REJ09B0027-0500