HD64F3687HV Datasheet, PDF (363/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 17 I²C Bus Interface 2 (IIC2)
SCL
SDA
(Input)
MST
1
2
Bit 0 Bit 1
7
8
1
Bit 6 Bit 7 Bit 0
7
8
1
2
Bit 6 Bit 7
Bit 0
TRS
RDRF
ICDRS
Data 1
Data 2
Data 3
ICDRR
User
processing ^{[2] Set MST}
(when outputting the clock)
Data 1
[3] Read ICDRR
Figure 17.15 Receive Mode Operation Timing
Data 2
[3] Read ICDRR
17.4.7 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 17.16 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
SCL or SDA
input signal
Sampling clock
C
D
Q
Latch
C
D
Q
Latch
March detector
Internal
SCL or SDA
signal
Sampling
clock
System clock
period
Figure 17.16 Block Diagram of Noise Conceler
Rev.5.00 Nov. 02, 2005 Page 329 of 500
REJ09B0027-0500