HD64F3687HV Datasheet, PDF (278/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
3. Contention between GR Write and Compare Match: If a compare match occurs in the T₂ state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure
13.54 shows the timing in this case.
GR write cycle
T1
T2
φ
GR address
WGR
(internal write signal)
TCNT
N
N+1
GR
N
M
GR write data
Compare match
signal
Disabled
Figure 13.54 Contention between GR Write and Compare Match
Rev.5.00 Nov. 02, 2005 Page 244 of 500
REJ09B0027-0500