HD64F3687HV Datasheet, PDF (240/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 13 Timer Z
2. Output compare timing
The compare match signal is generated in the last state in which TCNT and GR match (when
TCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TIOR is output at the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is
generated only after the next TCNT input clock pulse is input.
Figure 13.15 shows an example of the output compare timing.
φ
TCNT input
TCNT
GR
Compare match
signal
FTIOA to FTIOD
N
N+1
N
Figure 13.15 Output Compare Timing
Rev.5.00 Nov. 02, 2005 Page 206 of 500
REJ09B0027-0500