HD64F3687HV Datasheet, PDF (340/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 17 I²C Bus Interface 2 (IIC2)
• I²C bus receive data register (ICDRR)
• I²C bus shift register (ICDRS)
17.3.1 I²C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I²C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Initial
Bit
Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to
port function.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
6
RCVD
0
R/W Reception Disable
This bit enables or disables the next operation when TRS
is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
5
MST
0
R/W Master/Slave Select
4
TRS
0
R/W Transmit/Receive Select
In master mode with the I²C bus format, when arbitration
is lost, MST and TRS are both reset by hardware,
causing a transition to slave receive mode. Modification
of the TRS bit should be made between transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data agree
with the slave address that is set to SAR and the eighth
bit is 1, TRS is automatically set to 1. If an overrun error
occurs in master mode with the clock synchronous serial
format, MST is cleared to 0 and slave receive mode is
entered.
Operating modes are described below according to MST
and TRS combination. When clocked synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Rev.5.00 Nov. 02, 2005 Page 306 of 500
REJ09B0027-0500