HD64F3687HV Datasheet, PDF (82/538 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 3 Exception Handling
3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1 Exception Sources and Vector Address
Relative Module
RES pin
Watchdog timer

External interrupt
pin
CPU
Address break
CPU
External interrupt
pin
RTC

Timer V
SCI3
Exception Sources
Reset
Vector
Number
0
Reserved for system use
NMI
1 to 6
7
Trap instruction (#0)
8
(#1)
9
(#2)
10
(#3)
11
Break conditions satisfied
12
Direct transition by executing 13
the SLEEP instruction
IRQ0
14
Low-voltage detection
interrupt*
IRQ1
15
IRQ2
16
IRQ3
17
WKP
18
Overflow
19
Reserved for system use
20
Timer V compare match A
22
Timer V compare match B
Timer V overflow
SCI3 receive data full
23
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
Vector Address
H'0000 to H'0001
Priority
High
H'0002 to H'000D
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0014 to H'0015
H'0016 to H'0017
H'0018 to H'0019
H'001A to H'001B
H'001C to H'001D
H'001E to H'001F
H'0020 to H'0021
H'0022 to H'0023
H'0024 to H'0025
H'0026 to H'0027
H'0028 to H'0029
H'002C to H'002D
H'002E to H'002F
Low
Rev.5.00 Nov. 02, 2005 Page 48 of 500
REJ09B0027-0500