SAA7118 Datasheet, PDF (98/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

REGISTER FUNCTION
X-port I/O enable and output
clock phase control
I-port signal definitions
I-port signal polarities
I-port FIFO flag control and
arbitration
I-port I/O enable, output clock
and gated clock phase control
Power save/ADC-port control
Reserved
Status information scaler part
SUB
ADDR.
(HEX)
83
84
85
86
87
88
89 to 8E
8F
D7
(1)
IDG01
ISWP1
VITX1
IPCK3
DOSL1
(1)
XTRI
TASK A DEFINITION: REGISTERS 90H TO BFH
Basic settings and acquisition window definition
Task handling control
90
X-port formats and configuration 91
X-port input reference signal
92
definition
I-port output formats and
93
configuration
Horizontal input window start
94
95
Horizontal input window length
96
97
Vertical input window start
98
99
Vertical input window length
9A
9B
Horizontal output window length 9C
9D
Vertical output window length
9E
9F
CONLH
CONLV
XFDV
ICODE
XO7
(1)
XS7
(1)
YO7
(1)
YS7
(1)
XD7
(1)
YD7
(1)
D6
(1)
IDG00
ISWP0
VITX0
IPCK2
DOSL0
(1)
ITRI
D5
XPCK1
IDG11
ILLV
IDG02
IPCK1
SWRST
(1)
FFIL
D4
XPCK0
IDG10
IG0P
IDG12
IPCK0
DPROG
(1)
FFOV
D3
(1)
IDV1
IG1P
FFL1
(1)
SLM3
(1)
PRDON
OFIDC
HLDFV
XFDH
FSKP2
SCSRC1
XDV1
FSKP1
SCSRC0
XDV0
FSKP0
SCRQE
XCODE
I8_16
FYSK
FOI1
FOI0
XO6
(1)
XS6
(1)
YO6
(1)
YS6
(1)
XD6
(1)
YD6
(1)
XO5
(1)
XS5
(1)
YO5
(1)
YS5
(1)
XD5
(1)
YD5
(1)
XO4
(1)
XS4
(1)
YO4
(1)
YS4
(1)
XD4
(1)
YD4
(1)
XO3
XO11
XS3
XS11
YO3
YO11
YS3
YS11
XD3
XD11
YD3
YD11
D2
XRQT
IDV0
IRVP
FFL0
(1)
(1)
(1)
ERROF
RPTSK
FSC2
XDH
FSI2
XO2
XO10
XS2
XS10
YO2
YO10
YS2
YS10
XD2
XD10
YD2
YD10
D1
XPE1
IDH1
IRHP
FEL1
IPE1
SLM1
(1)
FIDSCI
STRC1
FSC1
XDQ
FSI1
XO1
XO9
XS1
XS9
YO1
YO9
YS1
YS9
XD1
XD9
YD1
YD9
D0
XPE0
IDH0
IDQP
FEL0
IPE0
SLM0
(1)
FIDSCO
STRC0
FSC0
XCKS
FSI0
XO0
XO8
XS0
XS8
YO0
YO8
YS0
YS8
XD0
XD8
YD0
YD8