SAA7118 Datasheet, PDF (44/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
ITU counting
622 623 624 625 1
2
3
4
5
6
7
. . . 22 23
single field counting 309 310 311 312 1
2
3
4
5
6
7
. . . 22 23
CVBS
HREF
F_ITU656
V123⁽¹⁾
VGATE
VSTO[8:0] = 134H
FID
(a) 1st field
VSTA[8:0] = 15H
ITU counting
309 310 311 312 313 314 315 316 317 318 319 . . . 335 336
single field counting 309 310 311 312 313 1
2
3
4
5
6
. . . 22 23
CVBS
HREF
F_ITU656
V123⁽¹⁾
VGATE
FID
VSTO[8:0] = 134H
(b) 2nd field
VSTA[8:0] = 15H
MHB540
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during
the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field
is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a
few clock cycles from version to version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table:
NAME
RTS0
RTS1
HREF
X
X
F_ITU656
−
−
V123
X
X
VGATE
X
X
FID
X
X
For further information see Section 15.2: Tables 56, 57 and 58.
XRH
X
−
−
−
−
XRV
−
X
X
−
−
Fig.28 Vertical timing diagram for 50 Hz/625 line systems.
2001 May 30
44