SAA7118 Datasheet, PDF (128/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
15.2.20 SUBADDRESS 13H
Table 58 RT/X-port output control; 13H[7:0]
BIT
DESCRIPTION
D7 RTCO output enable
D6 X-port XRH output
selection
D[5:4] X-port XRV output
selection
D3 horizontal lock indicator
selection
D[2:0] XPD7 to XPD0 (port
output format selection);
see Section 9.5
SYMBOL VALUE
FUNCTION
RTCE
0 3-state
1 enabled
XRHS
0 HREF (see Fig.30)
1 HS:
programmable width in LLC8 steps via HSB[7:0] 06H[7:0]
and HSS[7:0] 07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0]
11H[5:4] (see Fig.30)
XRVS[1:0] 00 V123 (see Figs 28 and 29)
01 ITU 656 related field ID (see Figs 28 and 29)
10 inverted V123
11 inverted ITU 656 related field ID
HLSEL
0 copy of inverted HLCK status bit (default)
1 fast horizontal lock indicator (for special applications only)
OFTS[2:0] 000 ITU 656
001 ITU 656 like format with modified field blanking according to
VGATE position (programmable via VSTA[8:0] 17H[0]
15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]])
010 Y-C_B-C_R 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted)
011 reserved
100 multiplexed AD2/AD1 or AD4/AD3 bypass (bits 8 to 1)
dependent on mode settings (see Section 15.2.4); if two
ADCs are selected AD2/AD4 is output at CREF = 1 and
AD1/AD3 is output at CREF = 0
101 multiplexed AD2/AD1 or AD4/AD3 bypass (bits 7 to 0)
dependent on mode settings (see Section 15.2.4); if two
ADCs are selected AD2/AD4 is output at CREF = 1 and
AD1/AD3 is output at CREF = 0
110 reserved
111 multiplexed ADC MSB/LSB bypass dependent on mode
settings; only one ADC should be selected at a time;
ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0
are outputs at CREF0
2001 May 30
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