SAA7118 Datasheet, PDF (145/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
Table 102 I-port FIFO flag control and arbitration; global set 86H[3:0]
X = don’t care.
I-PORT FIFO FLAG CONTROL AND ARBITRATION
FAE FIFO flag almost empty level
<16 Dwords
<8 Dwords
<4 Dwords
0 Dwords
FAF FIFO flag almost full level
≥16 Dwords
≥24 Dwords
≥28 Dwords
32 Dwords
CONTROL BITS D3 TO D0
FFL1
FFL0
FEL1
FEL0
X
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
Table 103 I-port I/O enable, output clock and gated clock phase control; global set 87H[7:4]
OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL
CONTROL BITS D7 TO D4⁽¹⁾
IPCK3⁽²⁾ IPCK2⁽²⁾ IPCK1 IPCK0
ICLK default output phase
X
X
0
0
ICLK phase shifted by ¹â„₂ clock cycle ⇒ recommended for ICKS1 = 1
X
X
0
1
and ICKS0 = 0 (subaddress 80H)
ICLK phase shifted by approximately 3 ns
X
X
1
0
ICLK phase shifted by ¹â„₂ clock cycle + approximately
3 ns ⇒ alternatively to setting ‘01’
X
X
1
1
IDQ = gated clock default output phase
0
0
X
X
IDQ = gated clock phase shifted by ¹â„₂ clock cycle ⇒ recommended
0
1
X
X
for gated clock output
IDQ = gated clock phase shifted by approximately 3 ns
1
0
X
X
IDQ = gated clock phase shifted by ¹â„₂ clock cycle + approximately
1
1
X
X
3 ns ⇒ alternatively to setting ‘01’
Notes
1. X = don’t care.
2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1).
Table 104 I-port I/O enable, output clock and gated clock phase control; global set 87H[1:0]
I-PORT I/O ENABLE
I-port output is disabled by software
I-port output is enabled by software
I-port output is enabled by pin ITRI at logic 0
I-port output is enabled by pin ITRI at logic 1
CONTROL BITS D1 AND D0
IPE1
IPE0
0
0
0
1
1
0
1
1
2001 May 30
145