SAA7118 Datasheet, PDF (36/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
8.1.4 CLOCK GENERATION CIRCUIT
The internal CGC generates all clock signals required for
the video input processor.
The internal signal LFCO is a digital-to-analog converted
signal provided by the horizontal PLL. It is the multiple of
the line frequency:
6.75 MHz = 429 × f_H (50 Hz), or
6.75 MHz = 432 × f_H (60 Hz).
The LFCO signal is multiplied by a factor of 2 and 4 in the
internal PLL circuit (including phase detector, loop filtering,
VCO and frequency divider) to obtain the output clock
signals. The rectangular output clocks have a 50% duty
factor.
Table 3 Decoder clock frequencies
CLOCK
XTALO
LLC
LLC2
LLC4 (internal)
LLC8 (virtual)
FREQUENCY (MHz)
24.576 or 32.110
27
13.5
6.75
3.375
LFCO
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
OSCILLATOR
LLC
DIVIDER
1/2
DIVIDER
1/2
MHB330
LLC2
Fig.21 Block diagram of the clock generation circuit.
8.1.5 POWER-ON RESET AND CHIP ENABLE (CE) INPUT
A missing clock, insufficient digital or analog V_DDA0 supply voltages (below 2.8 V) will start the reset sequence; all outputs
are forced to 3-state (see Fig.22). The indicator output RES is LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV system.
It is possible to force a reset by pulling the Chip Enable pin (CE) to ground. After the rising edge of CE and sufficient
power supply voltage, the outputs LLC, LLC2 and SDA return from 3-state to active, while the other signals have to be
activated via programming.
2001 May 30
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