SAA7118 Datasheet, PDF (95/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Table 37 I²C-bus receiver/transmitter overview
SUB
REGISTER FUNCTION
ADDR.
D7
(HEX)
Chip version: register 00H
Chip version (read only)
00
ID7
Video decoder: registers 01H to 1FH
FRONT-END PART: REGISTERS 01H TO 05H
Increment delay
01
Analog input control 1
02
Analog input control 2
03
Analog input control 3
04
Analog input control 4
05
DECODER PART: REGISTERS 06H TO 1FH
Horizontal sync start
06
Horizontal sync stop
07
Sync control
08
Luminance control
09
Luminance brightness control
0A
Luminance contrast control
0B
Chrominance saturation control 0C
Chrominance hue control
0D
Chrominance control 1
0E
Chrominance gain control
0F
Chrominance control 2
10
Mode/delay control
11
RT signal control
12
RT/X-port output control
13
Analog/ADC/compatibility
14
control
VGATE start, FID change
15
VGATE stop
16
(1)
FUSE1
(1)
GAI17
GAI27
HSB7
HSS7
AUFD
BYPS
DBRI7
DCON7
DSAT7
HUEC7
CDTO
ACGC
OFFU1
COLO
RTSE13
RTCE
CM99
VSTA7
VSTO7
D6
ID6
WPOFF
FUSE0
HLNRS
GAI16
GAI26
HSB6
HSS6
FSEL
YCOMB
DBRI6
DCON6
DSAT6
HUEC6
CSTD2
CGAIN6
OFFU0
RTP1
RTSE12
XRHS
UPTCV
VSTA6
VSTO6
D5
ID5
GUDL1
MODE5
VBSL
GAI15
GAI25
HSB5
HSS5
FOET
LDEL
DBRI5
DCON5
DSAT5
HUEC5
CSTD1
CGAIN5
OFFV1
HDEL1
RTSE11
XRVS1
AOSL1
VSTA5
VSTO5
D4
ID4
GUDL0
MODE4
CPOFF
GAI14
GAI24
HSB4
HSS4
HTC1
LUBW
DBRI4
DCON4
DSAT4
HUEC4
CSTD0
CGAIN4
OFFV0
HDEL0
RTSE10
XRVS0
AOSL0
VSTA4
VSTO4
D3
−
IDEL3
MODE3
HOLDG
GAI13
GAI23
HSB3
HSS3
HTC0
LUFI3
DBRI3
DCON3
DSAT3
HUEC3
DCVF
CGAIN3
CHBW
RTP0
RTSE03
HLSEL
XTOUTE
VSTA3
VSTO3
D2
−
IDEL2
MODE2
GAFIX
GAI12
GAI22
HSB2
HSS2
HPLL
LUFI2
DBRI2
DCON2
DSAT2
HUEC2
FCTC
CGAIN2
LCBW2
YDEL2
RTSE02
OFTS2
AUTO1
VSTA2
VSTO2
D1
−
IDEL1
MODE1
GAI28
GAI11
GAI21
HSB1
HSS1
VNOI1
LUFI1
DBRI1
DCON1
DSAT1
HUEC1
AUTO0
CGAIN1
LCBW1
YDEL1
RTSE01
OFTS1
APCK1
VSTA1
VSTO1
D0
−
IDEL0
MODE0
GAI18
GAI10
GAI20
HSB0
HSS0
VNOI0
LUFI0
DBRI0
DCON0
DSAT0
HUEC0
CCOMB
CGAIN0
LCBW0
YDEL0
RTSE00
OFTS0
APCK0
VSTA0
VSTO0