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SAA7118 Datasheet, PDF (161/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input | |||
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Philips Semiconductors
Multistandard video decoder with adaptive
comb ï¬lter and component video input
Preliminary speciï¬cation
SAA7118
16.4 Data slicer and data type control part
The given values force the following behaviour of the SAA7118 VBI-data slicer part:
⢠Closed captioning data are expected at line 21 of field 1 (60 Hz/525 line system)
⢠All other lines are processed as active video
⢠Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3EH â MSB of SAV/EAV = 1).
Table 142 Data slicer start set-up values
SUB
ADDRESS
(HEX)
REGISTER FUNCTION
BIT NAME(1)
START VALUES
7 6 5 4 3 2 1 0 HEX
40
slicer control 1
X, HAM_N, FCE, HUNT_N, X, X, X, 0 1 0 0 0 0 0 0 40
X
41 to 53 line control register 2 to 20 LCRn_7 to LCRn_0 (n = 2 to 20) 1 1 1 1 1 1 1 1 FF
54
line control register 21
LCR21_7 to LCR21_0
0 1 0 1 1 1 1 1 5F
55 to 57 line control register 22 to 24 LCRn_7 to LCRn_0 (n = 22 to 24) 1 1 1 1 1 1 1 1 FF
58
programmable framing code FC7 to FC0
0 0 0 0 0 0 0 0 00
59
horizontal offset for slicer
HOFF7 to HOFF0
5A
vertical offset for slicer
VOFF7 to VOFF0
5B
ï¬eld offset and MSBs for
FOFF, RECODE, X, VOFF8, X,
horizontal and vertical offset HOFF10 to HOFF8
0 1 0 0 0 1 1 1 47
0 0 0 0 0 1 1 0 06(2)
1 0 0 0 0 0 1 1 83(2)
5C
reserved
X, X, X, X, X, X, X, X
0 0 0 0 0 0 0 0 00
5D
header and data
FVREF, X, DID5 to DID0
identiï¬cation code control
0 0 1 1 1 1 1 0 3E
5E
sliced data identiï¬cation code X, X, SDID5 to SDID0
0 0 0 0 0 0 0 0 00
5F
reserved
X, X, X, X, X, X, X, X
0 0 0 0 0 0 0 0 00
60
slicer status byte 0
61
slicer status byte 1
â, FC8V, FC7V, VPSV, PPV, CCV,
â, â
â, â, F21_N, LN8 to LN4
read-only register
read-only register
62
slicer status byte 2
LN3 to LN0, DT3 to DT0
read-only register
Notes
1. All X values must be set to logic 0.
2. Changes for 50 Hz/625 line systems: subaddress 5AH = 03H and subaddress 5BH = 03H.
2001 May 30
161
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