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SAA7118 Datasheet, PDF (127/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input | |||
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Philips Semiconductors
Multistandard video decoder with adaptive
comb ï¬lter and component video input
Preliminary speciï¬cation
SAA7118
Table 57 RT signal control: RTS1 output; 12H[7:4]
The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]].
RTS1 OUTPUT
3-state
Constant LOW
CREF (13.5 MHz toggling pulse; see Fig.30)
CREF2 (6.75 MHz toggling pulse; see Fig.30)
HL; horizontal lock indicator (note 1):
HL = 0: unlocked
HL = 1: locked
VL; vertical and horizontal lock:
VL = 0: unlocked
VL = 1: locked
DL; vertical and horizontal lock and colour detected:
DL = 0: unlocked
DL = 1: locked
Reserved
HREF, horizontal reference signal; indicates 720 pixels valid data on the
expansion port. The positive slope marks the beginning of a new active
line. HREF is also generated during the vertical blanking interval
(see Fig.30).
HS:
programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0]
07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]
(see Fig.30)
HQ; HREF gated with VGATE
Reserved
V123; vertical sync (see vertical timing diagrams Figs 28 and 29)
VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1]
16H[7:0] and VGPS[17H[2]]
Reserved
FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical
timing diagrams Figs 28 and 29
RTSE13 RTSE12 RTSE11 RTSE10
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Note
1. Function of HL is selectable via HLSEL[13H[3]]:
a) HLSEL = 0: HL is standard horizontal lock indicator.
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.
VCRs).
2001 May 30
127
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