SAA7118 Datasheet, PDF (102/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

SUB
REGISTER FUNCTION
ADDR.
D7
D6
D5
D4
D3
(HEX)
Vertical chrominance phase
offset ‘00’
Vertical chrominance phase
offset ‘01’
Vertical chrominance phase
offset ‘10’
Vertical chrominance phase
offset ‘11’
Vertical luminance phase
offset ‘00’
Vertical luminance phase
offset ‘01’
Vertical luminance phase
offset ‘10’
Vertical luminance phase
offset ‘11’
E8
YPC07
YPC06
YPC05
YPC04
YPC03
E9
YPC17
YPC16
YPC15
YPC14
YPC13
EA
YPC27
YPC26
YPC25
YPC24
YPC23
EB
YPC37
YPC36
YPC35
YPC34
YPC33
EC
YPY07
YPY06
YPY05
YPY04
YPY03
ED
YPY17
YPY16
YPY15
YPY14
YPY13
EE
YPY27
YPY26
YPY25
YPY24
YPY23
EF
YPY37
YPY36
YPY35
YPY34
YPY33
Note
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
D2
YPC02
YPC12
YPC22
YPC32
YPY02
YPY12
YPY22
YPY32
D1
YPC01
YPC11
YPC21
YPC31
YPY01
YPY11
YPY21
YPY31
D0
YPC00
YPC10
YPC20
YPC30
YPY00
YPY10
YPY20
YPY30