SAA7118 Datasheet, PDF (153/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
15.7.9 SUBADDRESSES A0H TO A2H
Table 123 Horizontal prescaling; register set A [A0H[5:0]] and B [D0H[5:0]]
HORIZONTAL INTEGER PRESCALING RATIO (XPSC)
Not allowed
Downscale = 1
Downscale = ¹â„₂
...
Downscale = ¹â„₆₃
CONTROL BITS D5 TO D0
XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
...
...
...
...
...
...
1
1
1
1
1
1
Table 124 Accumulation length; register set A [A1H[5:0]] and B [D1H[5:0]]
HORIZONTAL PRESCALER ACCUMULATION
SEQUENCE LENGTH (XACL)
Accumulation length = 1
Accumulation length = 2
...
Accumulation length = 64
CONTROL BITS D5 TO D0
XACL5 XACL4 XACL3 XACL2 XACL1 XACL0
0
0
0
0
0
0
0
0
0
0
0
1
...
...
...
...
...
...
1
1
1
1
1
1
Table 125 Prescaler DC gain and FIR prefilter control; register set A [A2H[7:4]] and B [D2H[7:4]]
X = don’t care.
FIR PREFILTER CONTROL
Luminance FIR filter bypassed
H_y(z) = ¹â„₄ (1 2 1)
H_y(z) = ¹â„₈ (−1 1 1.75 4.5 1.75 1 −1)
H_y(z) = ¹â„₈ (1 2 2 2 1)
Chrominance FIR filter bypassed
H_uv(z) = ¹â„₄ (1 2 1)
H_uv(z) = ¹â„₃₂ (3 8 10 8 3)
H_uv(z) = ¹â„₈ (1 2 2 2 1)
CONTROL BITS D7 TO D4
PFUV1 PFUV0 PFY1 PFY0
X
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
2001 May 30
153