SAA7118 Datasheet, PDF (20/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
8.1.1.1 Clamping
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the four ADC channels are fixed for luminance (120),
chrominance (256) and for component inputs as
component Y (32), components P_B and P_R (256) or
components RGB (32). Clamping time in normal use is set
with the HCL pulse on the back porch of the video signal.
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
Component inputs are gain adjusted manually at a fixed
gain. The AGC active time is the sync bottom of the video
signal.
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 9 and 10) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
8.1.1.2 Gain control
The gain control circuit receives (via the I²C-bus) the static
gain levels for the four analog amplifiers or controls one of
these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO).
handbook, halfpage
511
120
1
TV line
analog line blanking
GAIN CLAMP
HSY
HCL
MHB726
Fig.6 Analog line with clamp (HCL) and gain
range (HSY).
analog input level
+3 dB
0 dB
(1 V (p-p) 18/56 Ω)
−6 dB
maximum
range 9 dB
minimum
controlled
ADC input level
0 dB
MHB325
Fig.7 Automatic gain range.
2001 May 30
20