SAA7118 Datasheet, PDF (160/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
16.3 Audio clock generation part
The given values force the following behaviour of the SAA7118 audio clock generation part:
• Used crystal is 24.576 MHz
• Expected field frequency is 59.94 Hz (e.g. NTSC M standard)
• Generated audio master clock frequency at pin AMCLK is 256 × 44.1 kHz = 11.2896 MHz
• AMCLK is externally connected to AMXCLK [short-cut between pins P11 (72) and M12 (76)]
• ASCLK = 32 × 44.1 kHz = 1.4112 MHz
• ALRCLK is 44.1 kHz.
Table 141 Audio clock part set-up values
SUB
ADDRESS
(HEX)
REGISTER FUNCTION
30
audio master clock cycles per
field; bits 7 to 0
31
audio master clock cycles per
field; bits 15 to 8
32
audio master clock cycles per
field; bits 17 and 16
33
reserved
34
audio master clock nominal
increment; bits 7 to 0
35
audio master clock nominal
increment; bits 15 to 8
36
audio master clock nominal
increment; bits 21 to 16
37
reserved
38
clock ratio AMXCLK to ASCLK
39
clock ratio ASCLK to ALRCLK
3A
audio clock generator basic
set-up
3B to 3F reserved
Note
1. All X values must be set to logic 0.
BIT NAME⁽¹⁾
ACPF7 to ACPF0
ACPF15 to ACPF8
X, X, X, X, X, X, ACPF17
and ACPF16
X, X, X, X, X, X, X, X
ACNI7 to ACNI0
ACNI15 to ACNI8
X, X, ACNI21 to ACNI16
X, X, X, X, X, X, X, X
X, X, SDIV5 to SDIV0
X, X, LRDIV5 to LRDIV0
X, X, X, X, APLL, AMVR, LRPH,
SCPH
X, X, X, X, X, X, X, X
START VALUES
7 6 5 4 3 2 1 0 HEX
1 0 1 1 1 1 0 0 BC
1 1 0 1 1 1 1 1 DF
0 0 0 0 0 0 1 0 02
0 0 0 0 0 0 0 0 00
1 1 0 0 1 1 0 1 CD
1 1 0 0 1 1 0 0 CC
0 0 1 1 1 0 1 0 3A
0 0 0 0 0 0 0 0 00
0 0 0 0 0 0 1 1 03
0 0 0 1 0 0 0 0 10
0 0 0 0 0 0 0 0 00
0 0 0 0 0 0 0 0 00
2001 May 30
160