SAA7118 Datasheet, PDF (138/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
15.5.2 SUBADDRESSES 34H TO 36H
Table 78 Audio master clock (AMCLK) nominal increment
SUBADDRESS
34H
35H
36H
ACNI7
ACNI15
−
ACNI6
ACNI14
−
CONTROL BITS D7 TO D0
ACNI5
ACNI4
ACNI3
ACNI2
ACNI13 ACNI12 ACNI11 ACNI10
ACNI21 ACNI20 ACNI19 ACNI18
ACNI1
ACNI9
ACNI17
ACNI0
ACNI8
ACNI16
15.5.3 SUBADDRESS 38H
Table 79 Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK)
SUBADDRESS
38H
−
CONTROL BITS D7 TO D0
−
SDIV5
SDIV4
SDIV3
SDIV2
SDIV1
SDIV0
15.5.4 SUBADDRESS 39H
Table 80 Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK)
SUBADDRESS
39H
−
CONTROL BITS D7 TO D0
−
LRDIV5 LRDIV4 LRDIV3 LRDIV2
LRDIV1
LRDIV0
15.5.5 SUBADDRESS 3AH
Table 81 Audio clock control; 3AH[3:0]
BIT
DESCRIPTION
D3 audio PLL modes
D2 audio master clock
vertical reference
D1 ALRCLK phase
D0 ASCLK phase
SYMBOL VALUE
FUNCTION
APLL
0 PLL active, AMCLK is field-locked
1 PLL open, AMCLK is free-running
AMVR
0 vertical reference pulse is taken from internal decoder
1 vertical reference is taken from XRV input (expansion port)
LRPH
0 ALRCLK edges triggered by falling edges of ASCLK
1 ALRCLK edges triggered by rising edges of ASCLK
SCPH
0 ASCLK edges triggered by falling edges of AMCLK
1 ASCLK edges triggered by rising edges of AMCLK
15.6 Programming register VBI-data slicer
15.6.1 SUBADDRESS 40H
Table 82 Slicer control 1; 40H[6:4]
BIT
DESCRIPTION
D6 Hamming check
D5 framing code error
D4 amplitude searching
SYMBOL VALUE
FUNCTION
HAM_N
0 Hamming check for 2 bytes after framing code,
dependent on data type (default)
1 no Hamming check
FCE
0 one framing code error allowed
1 no framing code errors allowed
HUNT_N 0 amplitude searching active (default)
1 amplitude searching stopped
2001 May 30
138