SAA7118 Datasheet, PDF (135/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
15.3.4 SUBADDRESS 29H
Table 70 Component delay/fast switch control; 29H[7:0]
BIT
DESCRIPTION
SYMBOL VALUE
FUNCTION
D7 fast switch enable
FSWE
0 disabled
1 pixelwise switching between decoded CVBS signal and
component input signal is enabled (should only be used for
component sources synchronous to CVBS input)
D6 fast switch input
polarity if FSWE = 1
FSWI
0 FSW = 0: decoded CVBS signal, FSW = 1: component signal
1 FSW = 1: decoded CVBS signal, FSW = 0: component signal
static selection if
FSWE = 0
0 for modes 00H to 1FH
1 for modes 20H to 3FH
D[5:4] fast switch input delay FSWDL[1:0] 00 0 pixel (default)
adjustment relative to
component input
signal
01 +1 pixel
10 −2 pixel
11 −1 pixel
D3 component luminance
peaking
CMFI
0 disabled
1 enabled (+1.5 dB at 5 MHz)
D[2:0] component input delay
adjustment relative to
decoded CVBS signal
CPDL[2:0]
000 0 pixel (default)
001 +4 pixel
010 +8 pixel
011 +12 pixel
100 −16 pixel
101 −12 pixel
110 −8 pixel
111 −4 pixel
15.3.5 SUBADDRESS 2AH
Table 71 Luminance brightness control component part; 2AH[7:0]
OFFSET
255 (bright)
128 (ITU level)
0 (dark)
CBRI7
1
1
0
CBRI6
1
0
0
CONTROL BITS D7 TO D0
CBRI5
1
0
0
CBRI4
1
0
0
CBRI3
1
0
0
CBRI2
1
0
0
CBRI1
1
0
0
CBRI0
1
0
0
2001 May 30
135