SAA7118 Datasheet, PDF (142/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
Table 93 Global control 1; global set 80H[3:0]
X = don’t care.
I-PORT AND SCALER BACK-END CLOCK SELECTION
ICLK output and back-end clock is line-locked clock LLC from decoder
ICLK output and back-end clock is XCLK from X-port
ICLK output is LLC and back-end clock is LLC2 clock
Back-end clock is the ICLK input
IDQ pin carries the data qualifier
IDQ pin carries a gated back-end clock (DQ AND CLK)
IDQ generation only for valid data
IDQ qualifies valid data inside the scaling region and all data outside the scaling
region
CONTROL BITS D3 TO D0
ICKS3 ICKS2 ICKS1 ICKS0
X
X
0
0
X
X
0
1
X
X⁽¹⁾
1
0
X
X
1
1
X
0
X
X
X
1
X
X
0
X
X
X
1
X
X
X
Note
1. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
15.7.2 SUBADDRESSES 83H TO 87H
Table 94 X-port I/O enable and output clock phase control; global set 83H[5:4]
OUTPUT CLOCK PHASE CONTROL
XCLK default output phase, recommended value
XCLK output inverted
XCLK phase shifted by approximately 3 ns
XCLK output inverted and shifted by approximately 3 ns
CONTROL BITS D5 AND D4
XPCK1
XPCK0
0
0
0
1
1
0
1
1
Table 95 X-port I/O enable and output clock phase control; global set 83H[2:0]
X = don’t care.
X-PORT I/O ENABLE
X-port output is disabled by software
X-port output is enabled by software
X-port output is enabled by pin XTRI at logic 0
X-port output is enabled by pin XTRI at logic 1
XRDY output signal is A/B task flag from event handler (A = 1)
XRDY output signal is ready signal from scaler path (XRDY = 1 means the
SAA7118 is ready to receive data)
CONTROL BITS D2 TO D0
XRQT
X
X
X
X
0
1
XPE1
0
0
1
1
X
X
XPE0
0
1
0
1
X
X
2001 May 30
142