SAA7118 Datasheet, PDF (8/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
PIN
SYMBOL
TYPE⁽¹⁾
QFP160 BGA156
DESCRIPTION
DNC13
39
N1
NC do not connect, reserved for future extensions and for testing
DNC14
40
N2
I/pu do not connect, reserved for future extensions and for testing
DNC18
41
P2
I/O do not connect, reserved for future extensions and for testing
DNC15
42
N3
I/pd do not connect, reserved for future extensions and for testing
EXMCLR 43
P3
I/pd external mode clear (with internal pull-down)
CE
44
N4
I/pu chip enable or reset input (with internal pull-up)
V_DDD1
LLC
45
C5
46
P4
P digital supply voltage 1 (peripheral cells)
O line-locked system clock output (27 MHz nominal)
V_SSD1
LLC2
RES
47
D5
P digital ground 1 (peripheral cells)
48
N5
O line-locked ¹â„₂ clock output (13.5 MHz nominal)
49
P5
O reset output (active LOW)
V_DDD2
50
C8
P digital supply voltage 2 (core)
V_SSD2
51
D7
P digital ground 2 (core; substrate connection)
CLKEXT 52
N6
I external clock input intended for analog-to-digital conversion of VSB
signals (36 MHz)
ADP8
53
P6
O MSB of direct analog-to-digital converted output data (VSB)
ADP7
ADP6
ADP5
ADP4
ADP3
V_DDD3
ADP2
ADP1
ADP0
54
M6
O MSB − 1 of direct analog-to-digital converted output data (VSB)
55
L6
O MSB − 2 of direct analog-to-digital converted output data (VSB)
56
N7
O MSB − 3 of direct analog-to-digital converted output data (VSB)
57
P7
O MSB − 4 of direct analog-to-digital converted output data (VSB)
58
L7
O MSB − 5 of direct analog-to-digital converted output data (VSB)
59
C9
P digital supply voltage 3 (peripheral cells)
60
M7
O MSB − 6 of direct analog-to-digital converted output data (VSB)
61
P8
O MSB − 7 of direct analog-to-digital converted output data (VSB)
62
N8
O LSB of direct analog-to-digital converted output data (VSB)
V_SSD3
63
D9
P digital ground 3 (peripheral cells)
INT_A
64
P9
O/od I²C-bus interrupt flag (LOW if any enabled status bit has changed)
V_DDD4
SCL
65
C10
P digital supply voltage 4 (core)
66
N9
I serial clock input (I²C-bus)
V_SSD4
SDA
67
D10
P digital ground 4 (core)
68
P10 I/O/od serial data input/output (I²C-bus)
RTS0
69
M10
O real-time status or sync information, controlled by subaddresses
11H and 12H
RTS1
70
N10
O real-time status or sync information, controlled by subaddresses
11H and 12H
RTCO
71
L10 O/st/pd real-time control output; contains information about actual system clock
frequency, field rate, odd/even sequence, decoder status, subcarrier
frequency and phase and PAL sequence (see document “RTC Functional
Description”, available on request); the RTCO pin is enabled via I²C-bus
bit RTCE; see notes 5, 6 and Table 35
AMCLK
72
P11
O audio master clock output, up to 50% of crystal clock
2001 May 30
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