SAA7118 Datasheet, PDF (35/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
+255
+209
white
+255
+199
white
LUMINANCE
LUMINANCE
+71
black
+60
black shoulder
SYNC
1
sync bottom
a. Sources containing 7.5 IRE black level offset
(e.g. NTSC M).
+60
black shoulder = black
SYNC
1
sync bottom
MGD700
b. Sources not containing black level offset.
CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128.
Equation for modification of the raw data levels via bytes RAWG and RAWO:
CVBS_OUT = Int ^{R-----A-6---W-4----G----} × (CVBS_nom – 128) + RAWO
It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”.
Fig.20 CVBS (raw data) range for scaler input, data slicer and X-port output.
8.1.3 SYNCHRONIZATION
The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz in a
low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided
clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals
(e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an
oscillator to generate the line frequency control signal LFCO; see Fig.21.
The detection of ‘pseudo syncs’ as part of the macrovision copy protection standard is also achieved within the
synchronization circuit.
The result is reported as flag COPRO within the decoder status byte at subaddress 1FH.
2001 May 30
35