SAA7118 Datasheet, PDF (73/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
9.5.1 X-PORT CONFIGURED AS OUTPUT
If data output is enabled at the expansion port, then the
data stream from the decoder is presented. The data
format of the 8-bit data bus is dependent on the chosen
data type, selectable by the line control registers
LCR2 to LCR24; see Table 4. In contrast to the image
port, the sliced data format is not available on the
expansion port. Instead, raw CVBS samples are always
transferred if any sliced data type is selected.
Some details of data types on the expansion port are as
follows:
• Active video (data type 15): contains component
Y-C_B-C_R 4 : 2 : 2 signal, 720 active pixels per line. The
amplitude and offsets are programmable via
DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to
DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. For
nominal levels see Fig.19.
• Test line (data type 6): is similar to the active video
format, with some constraints within the data
processing:
– adaptive chrominance comb filter, vertical filter
(chrominance comb filter for NTSC standards, PAL
phase error correction) within the chrominance
processing are disabled
– adaptive luminance comb filter, peaking and
chrominance trap are bypassed within the luminance
processing.
This data type is defined for future enhancements. It
could be activated for lines containing standard test
signals within the vertical blanking period. Currently the
most sources do not contain test lines. For nominal
levels see Fig.19.
• Raw samples (data types 0 to 5 and 7 to 14): C_B-C_R
samples are similar to data type 6, but CVBS samples
are transferred instead of processed luminance samples
within the Y time slots.
The amplitude and offset of the CVBS signal is
programmable via RAWG7 to RAWG0 and
RAWO7 to RAWO0; see Chapter 15, Tables 63 and 64.
For nominal levels see Fig.20.
The relationship of LCR programming to line numbers is
described in Section 8.3, see Tables 5 to 8.
The data type selections by LCR are overruled by setting
OFTS2 = 1 (subaddress 13H bit 2). This setting is mainly
intended for device production test. The VPO-bus carries
the upper or lower 8 bits of the two ADCs depending on the
OFTS[1:0] 13H[1:0] settings; see Table 58. The output
configuration is done via MODE[5:0] 02H[5:0] settings; see
Table 40. If a Y/C mode is selected, the expansion port
carries the multiplexed output signals of both ADCs, and in
CVBS mode the output of only one ADC. No timing
reference codes are generated in this mode.
Remark: The LSBs (bit 0) of the ADCs are also available
on pin RTS0; see Table 56.
The SAV/EAV timing reference codes define the start and
end of valid data regions. The ITU-blanking code
sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the
horizontal blanking period between EAV and SAV.
The position of the F-bit is constant in accordance with
ITU 656; see Tables 30 and 31.
The V-bit can be generated in two different ways
(see Tables 30 and 31) controlled via OFTS1 and OFTS0;
see Table 58.
The F and V bits change synchronously with the EAV
code.
Table 28 Data format on the expansion port
BLANKING
PERIOD
TIMING
REFERENCE
CODE (HEX)⁽¹⁾
720 PIXELS Y-C_B-C_R 4 : 2 : 2 DATA⁽²⁾
TIMING
REFERENCE
CODE (HEX)⁽¹⁾
BLANKING
PERIOD
... 80 10 FF 00 00 SAV C_B0 Y0 C_R0 Y1 C_B2 Y2 ... C_R718 Y719 FF 00 00 EAV 80 10 ...
Notes
1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to ‘010’, see Table 58. In this
event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values.
2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced
by CVBS samples.
2001 May 30
73