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| SAA7118 Datasheet, PDF (155/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input | |||
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Philips Semiconductors
Multistandard video decoder with adaptive
comb ï¬lter and component video input
Preliminary speciï¬cation
SAA7118
15.7.11 SUBADDRESSES A8H TO AEH
Table 130 Horizontal luminance scaling increment; register set A [A8H[7:0]; A9H[7:0]] and B [D8H[7:0]; D9H[7:0]]
CONTROL BITS
HORIZONTAL LUMINANCE
SCALING INCREMENT
Scale = 1024â1 (theoretical) zoom
Scale = 1024â294, lower limit deï¬ned by
data path structure
Scale = 1024â1023 zoom
Scale = 1, equals 1024
Scale = 1024â1025 downscale
Scale = 1024â8191 downscale
A [A9H[7:4]]
B [D9H[7:4]]
XSCY[15:12](1)
0000
0000
0000
0000
0000
0001
A [A9H[3:0]]
B [D9H[3:0]]
XSCY[11:8]
0000
0001
0011
0100
0100
1111
A [A8H[7:4]]
B [D8H[7:4]]
XSCY[7:4]
0000
0010
1111
0000
0000
1111
A [A8H[3:0]]
B [D8H[3:0]]
XSCY[3:0]
0000
0110
1111
0000
0001
1111
Note
1. Bits XSCY[15:13] are reserved and are set to logic 0.
Table 131 Horizontal luminance phase offset; register set A [AAH[7:0]] and B [DAH[7:0]]
HORIZONTAL LUMINANCE PHASE
OFFSET
Offset = 0
Offset = 1â32 pixel
Offset = 32â32 = 1 pixel
Offset = 255â32 pixel
CONTROL BITS D7 TO D0
XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 132 Horizontal chrominance scaling increment; register set A [ACH[7:0]; ADH[7:0]] and B [DCH[7:0]; DDH[7:0]]
HORIZONTAL CHROMINANCE
SCALING INCREMENT
This value must be set to the
luminance value 1â2XSCY[15:0]
A [ADH[7:4]]
B [DDH[7:4]]
XSCC[15:12](1)
0000
0000
0001
CONTROL BITS
A [ADH[3:0]]
B [DDH[3:0]]
A [ACH[7:4]]
B [DCH[7:4]]
XSCC[11:8]
XSCC[7:4]
0000
0000
1111
0000
0000
1111
A [ACH[3:0]]
B [DCH[3:0]]
XSCC[3:0]
0000
0001
1111
Note
1. Bits XSCC[15:13] are reserved and are set to logic 0.
2001 May 30
155
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