SAA7118 Datasheet, PDF (39/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
8.2.2 DOWNFORMATTER
The block mainly consists of 2 parts: the colour difference
signal downsampler and the Y-path.
The colour difference signals are first passed through
low-pass filters which reduce alias effects due to the lower
data rate. The ITU sampling scheme requires that both
colour difference samples fit to the first Y sample of the
current time slot. Thus the C_R signal is delayed by 1 clock
before it is fed to the multiplexer. The switch signal defines
the data multiplex phase at the output: a ‘0’ marks the first
clock of a time slot, this is a C_B sample. The output is fed
through a register, so that the multiplexer runs with the
opposite phase.
The delay compensation for the Y signal already provides
most of the registers required for a small high-pass filter. It
can be used to compensate high frequency losses in the
analog part. It provides 2 dB gain at 6.75 MHz.
The Y high-pass filter frequency response is shown in
Fig.26. The DC gain of the filter is 1, so a limiter is required
at the filter output. The current implementation clips at the
maximum values of 0 and 511. The entire filter can be
controlled by the I²C-bus bit CMFI in subaddress 29H.
handbook, full pagewidth
CR
CB
switch
Y
CMFI
LOW-PASS
DQ
LOW-PASS
0
DQ
(CR-CB)OUT
1
HIGH-PASS
bypass
delay compensation
n
DQ
YOUT
MHB732
Fig.24 Downformatter block diagram.
2001 May 30
39