SAA7118 Datasheet, PDF (46/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
CVBS input
expansion port
data output
burst
processing delay ADC to expansion port:
140 × 1/LLC
sync clipped
HREF (50 Hz)
CREF
720 × 2/LLC
CREF2
HS (50 Hz)
5 × 2/LLC
programming range 108
0
(step size: 8/LLC)
HREF (60 Hz)
CREF
720 × 2/LLC
CREF2
HS (60 Hz)
programming range ₁₀₇
(step size: 8/LLC)
1 × 2/LLC
0
12 × 2/LLC
144 × 2/LLC
2 × 2/LLC
−107
16 × 2/LLC
138 × 2/LLC
2 × 2/LLC
−106
MHB542
The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 15.2.19 Tables 56 and 57);
their polarity can be inverted via RTP0 and/or RTP1.
The signals HREF and HS are available on pin XRH (see Section 15.2.20 Table 58).
Fig.30 Horizontal timing diagram (50/60 Hz).
2001 May 30
46