SAA7118 Datasheet, PDF (150/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
Table 115 I-port output format and configuration; register set A [93H[7:5]] and B [C3H[7:5]]
X = don’t care.
I-PORT OUTPUT FORMATS AND CONFIGURATION
All lines will be output
Skip the number of leading Y only lines, as defined by FOI1 and FOI0
Dwords are transferred byte wise, see subaddress 85H bits ISWP1 and ISWP0
Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85H bits
ISWP1 and ISWP0
No ITU 656 like SAV/EAV codes are available
ITU 656 like SAV/EAV codes are inserted in the output data stream, framed by a
qualifier
CONTROL BITS D7 TO D5
ICODE
X
X
X
X
I8_16
X
X
0
1
FYSK
0
1
X
X
0
X
X
1
X
X
Table 116 I-port output format and configuration; register set A [93H[4:0]] and B [C3H[4:0]]
X = don’t care.
I-PORT OUTPUT FORMATS AND CONFIGURATION
4 : 2 : 2 Dword formatting
4 : 1 : 1 Dword formatting
4 : 2 : 0, only every 2nd line Y + C_B-C_R output, in between
Y only output
4 : 1 : 0, only every 4th line Y + C_B-C_R output, in between
Y only output
Y only
Not defined
Not defined
Not defined
No leading Y only line, before 1st Y + C_B-C_R line is output
1 leading Y only line, before 1st Y + C_B-C_R line is output
2 leading Y only lines, before 1st Y + C_B-C_R line is output
3 leading Y only lines, before 1st Y + C_B-C_R line is output
FOI1
X
X
X
X
X
X
X
X
0
0
1
1
CONTROL BITS D4 TO D0
FOI0
X
X
X
FSI2
0
0
0
FSI1
0
0
1
X
0
1
X
1
0
X
1
0
X
1
1
X
1
1
0
X
X
1
X
X
0
X
X
1
X
X
FSI0
0
1
0
1
0
1
0
1
X
X
X
X
2001 May 30
150