SAA7118 Datasheet, PDF (156/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
Table 133 Horizontal chrominance phase offset; register set A [AEH[7:0]] and B [DEH[7:0]]
HORIZONTAL CHROMINANCE
PHASE OFFSET
This value must be set to ¹â„₂XPHY[7:0]
XPHC7
0
0
1
XPHC6
0
0
1
CONTROL BITS D7 TO D0
XPHC5 XPHC4 XPHC3 XPHC2
0
0
0
0
0
0
0
0
1
1
1
1
XPHC1
0
0
1
XPHC0
0
1
1
15.7.12 SUBADDRESSES B0H TO BFH
Table 134 Vertical luminance scaling increment; register set A [B0H[7:0]; B1H[7:0]] and B [E0H[7:0]; E1H[7:0]]
CONTROL BITS
VERTICAL LUMINANCE SCALING
INCREMENT
A [B1H[7:4]]
B [E1H[7:4]]
A [B1H[3:0]]
B [E1H[3:0]]
A [B0H[7:4]]
B [E0H[7:4]]
A [B0H[3:0]]
B [E0H[3:0]]
Scale = ¹⁰²⁴⁄₁ (theoretical) zoom
Scale = ¹⁰²⁴⁄₁₀₂₃ zoom
Scale = 1, equals 1024
Scale = ¹⁰²⁴⁄₁₀₂₅ downscale
Scale = ¹â„_63.999 downscale
YSCY[15:12]
0000
0000
0000
0000
1111
YSCY[11:8]
0000
0011
0100
0100
1111
YSCY[7:4]
0000
1111
0000
0000
1111
YSCY[3:0]
0001
1111
0000
0001
1111
Table 135 Vertical chrominance scaling increment; register set A [B2H[7:0]; B3H[7:0]] and B [E2H[7:0]; E3H[7:0]]
CONTROL BITS
VERTICAL CHROMINANCE
SCALING INCREMENT
A [B3H[7:4]]
B [E3H[7:4]]
A [B3H[3:0]]
B [E3H[3:0]]
A [B2H[7:4]]
B [E2H[7:4]]
A [B2H[3:0]]
B [E2H[3:0]]
This value must be set to the
luminance value YSCY[15:0]
YSCC[15:12]
0000
1111
YSCC[11:8]
0000
1111
YSCC[7:4]
0000
1111
YSCC[3:0]
0001
1111
Table 136 Vertical scaling mode control; register set A [B4H[4 and 0]] and B [E4H[4 and 0]]
X = don’t care.
VERTICAL SCALING MODE CONTROL
CONTROL BITS D4 AND D0
YMIR
YMODE
Vertical scaling performs linear interpolation between lines
X
0
Vertical scaling performs higher order accumulating interpolation, better alias
X
1
suppression
No mirroring
0
X
Lines are mirrored
1
X
2001 May 30
156