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SAA7118 Datasheet, PDF (59/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input
Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
In Tables 13 and 14 PHO is a usable common phase
offset.
It should be noted that the equations of Fig.36 produce an
interpolated output, also for the unscaled case, as the
geometrical reference position for all conversions is the
position of the first line of the lower field (see Table 13).
If there is no need for UP-LO and LO-UP conversion and
the input field ID is the reference for the back-end
operation, then it is UP-LO = UP-UP and LO-UP = LO-LO
and the 1⁄2 line phase shift (PHO + 16) that can be
skipped. This case is listed in Table 14.
The SAA7118 supports 4 phase offset registers per task
and component (luminance and chrominance). The value
of 20H represents a phase shift of one line.
The registers are assigned to the following events;
e.g. subaddresses B8H to BBH:
• B8H: 00 = input field ID 0, task status bit 0 (toggle
status, see Section 8.4.1.3)
• B9H: 01 = input field ID 0, task status bit 1
• BAH: 10 = input field ID 1, task status bit 0
• BBH: 11 = input field ID 1, task status bit 1.
Depending on the input signal (interlaced or
non-interlaced) and the task processing 50 Hz or field
reduced processing with one or two tasks (see examples
in Section 8.4.1.3), other combinations may also be
possible, but the basic equations are the same.
Table 13 Examples for vertical phase offset usage: global equations
INPUT FIELD UNDER
PROCESSING
OUTPUT FIELD
INTERPRETATION
USED ABBREVIATION
EQUATION FOR PHASE OFFSET
CALCULATION (DECIMAL VALUES)
Upper input lines
upper output lines UP-UP
PHO + 16
Upper input lines
lower output lines UP-LO
PHO + Y-----S----C----Y6---4-[--1---5---:--0---] + 16
Lower input lines
upper output lines LO-UP
PHO
Lower input lines
lower output lines LO-LO
PHO + Y-----S----C----Y6---4-[--1---5---:--0---]
2001 May 30
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