SAA7118 Datasheet, PDF (70/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
9.2 Audio clock signals
The SAA7118 also synchronizes the audio clock and
sampling rate to the video frame rate, via a very slow PLL.
This ensures that the multimedia capture and compression
processes always gather the same predefined number of
samples per video frame.
An audio master clock AMCLK and two divided clocks
ASCLK and ALRCLK are generated;
• ASCLK: can be used as audio serial clock
• ALRCLK: audio left/right channel clock.
The ratios are programmable; see also Section 8.7.
Table 25 Audio clock pin description
SYMBOL PIN⁽¹⁾ I/O
DESCRIPTION
BIT
AMCLK
P11 O audio master clock output
(72)
ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] and
ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0]
AMXCLK M12 I external audio master clock input for the clock −
(76)
division circuit, can be directly connected to
output AMCLK for standard applications
ASCLK
N11 O serial audio clock output, can be synchronized SDIV[5:0] 38H[5:0] and SCPH[3AH[0]]
(74)
to rising or falling edge of AMXCLK
ALRCLK P12 O audio channel (left/right) clock output, can be LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]]
(75)
synchronized to rising or falling edge of ASCLK
Note
1. Pin numbers for QFP160 in parenthesis.
9.3 Clock and real-time synchronization signals
For the generation of the line-locked video (pixel) clock
LLC, and of the frame-locked audio serial bit clock, a
crystal accurate frequency reference is required. An
oscillator is built-in for fundamental or third harmonic
crystals. The supported crystal frequencies are
32.11 or 24.576 MHz (defined during reset by strapping
pin ALRCLK).
Alternatively pin XTALI can be driven from an external
single-ended oscillator.
The crystal oscillation can be propagated as a clock to
other ICs in the system via pin XTOUT.
The Line-Locked Clock (LLC) is the double pixel clock of
nominal 27 MHz. It is locked to the selected video input,
generating baseband video pixels according to “ITU
recommendation 601”. In order to support interfacing
circuits, a direct pixel clock (LLC2) is also provided.
The pins for line and field timing reference signals are
RTCO, RTS1 and RTS0. Various real-time status
information can be selected for the RTS pins. The signals
are always available (output) and reflect the
synchronization operation of the decoder part in the
SAA7118. The function of the RTS1 and RTS0 pins can
be defined by bits RTSE1[3:0] 12H[7:4] and RTSE0[3:0]
12H[3:0].
2001 May 30
70