SAA7118 Datasheet, PDF (146/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
15.7.3 SUBADDRESS 88H
Table 105 ADC-port control; global set 88H[7:4]
ADC-PORT OUTPUT CONTROL/START-UP CONTROL
DPROG = 0 after reset
DPROG = 1 can be used to assign that the device has been
programmed; this bit can be monitored in the scalers status byte,
bit PRDON; if DPROG was set to logic 1 and PRDON status bit
shows a logic 0 a power-up or start-up fail has occurred
Scaler path is reset to its idle state, software reset
Scaler is switched back to operation
Digitized ADC1 signal is fed to port ADP[8:0]
Digitized ADC2 signal is fed to port ADP[8:0]
Digitized ADC3 signal is fed to port ADP[8:0]
Digitized ADC4 signal is fed to port ADP[8:0]
Notes
1. X = don’t care.
2. Bit SWRST is now located here.
CONTROL BITS D7 TO D4⁽¹⁾
DOSL1 DOSL0 SWRST⁽²⁾ DPROG
X
X
X
0
X
X
X
1
X
X
0
X
X
X
1
X
0
0
X
X
0
1
X
X
1
0
X
X
1
1
X
X
Table 106 Power save control; global set 88H[3] and 88H[1:0]
X = don’t care.
POWER SAVE CONTROL
Decoder and VBI slicer are in operational mode
Decoder and VBI slicer are in power-down mode; scaler only operates, if scaler
input and ICLK source is the X-port (refer to subaddresses 80H and 91H/C1H)
Scaler is in operational mode
Scaler is in power-down mode; scaler in power-down stops I-port output
Audio clock generation active
Audio clock generation in power-down and output disabled
CONTROL BITS D3, D1 AND D0
SLM3
X
X
SLM1
X
X
SLM0
0
1
X
0
X
X
1
X
0
X
X
1
X
X
2001 May 30
146