SAA7118 Datasheet, PDF (162/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
16.5 Scaler and interfaces
Table 143 shows some examples for the scaler
programming with:
• prsc = prescale ratio
• fisc = fine scale ratio
• vsc = vertical scale ratio.
The ratio is defined as: _{n--n--u--u-m--m---b--b--e-e--r--r--o-o--f--f-o--i-n-u---pt--p-u--u--t-t--p--p-i--xi-x--e-e--l-l}
In the following settings the VBI-data slicer is inactive. To
activate the VBI-data slicer, VITX[1:0] 86H[7:6] has to be
set to ‘11’. Depending on the VBI-data slicer settings, the
sliced VBI-data is inserted after the end of the scaled video
lines, if the regions of VBI-data slicer and scaler overlaps.
To compensate the running-in of the vertical scaler, the
vertical input window lengths are extended by
2 to 290 lines, respectively 242 lines for XS, but the scaler
increment calculations are done with 288, respectively
240 lines.
16.5.1 TRIGGER CONDITION
For trigger condition STRC[1:0] 90H[1:0] not equal to ‘00’.
If the value of (YO + YS) is greater than or equal to 262
(NTSC), respectively 312 (PAL) the output field rate is
reduced to 30 Hz, respectively 25 Hz.
Horizontal and vertical offsets (XO and YO) have to be
used to adjust the displayed video in the display window.
As this adjustment is application dependent, the listed
values are only dummy values.
16.5.2 MAXIMUM ZOOM FACTOR
The maximum zoom factor is dependent on the back-end
data rate and therefore back-end clock and data format
dependent (8 or 16-bit output). The maximum horizontal
zoom is limited to approximately 3.5, due to internal data
path restrictions.
16.5.3 EXAMPLES
Table 143 Example of configurations
EXAMPLE
NUMBER
SCALER SOURCE AND REFERENCE EVENTS
INPUT OUTPUT
WINDOW WINDOW
SCALE
RATIOS
1
analog input to 8-bit I-port output, with SAV/EAV codes, 8-bit 720 × 240 720 × 240 prsc = 1;
serial byte stream decoder output at X-port; acquisition trigger
fisc = 1;
at falling edge vertical and rising edge horizontal reference
vsc = 1
signal; H and V-gates on IGPH and IGPV, IGP0 = VBI sliced
data flag, IGP1 = FIFO almost full, level ≥24, IDQ qualifier
logic 1 active
2
analog input to 16-bit output, without SAV/EAV codes, Y on
704 × 288 768 × 288 prsc = 1;
I-port, C_B-C_R on H-port and decoder output at X-port;
acquisition trigger at falling edge vertical and rising edge
fisc = 0.91667;
vsc = 1
horizontal reference signal; H and V-pulses on IGPH and IGPV,
output FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0
active
3
X-port input 8-bit with SAV/EAV codes, no reference signals on 720 × 240 352 × 288 prsc = 2;
XRH and XRV, XCLK as gated clock; field detection and
fisc = 1.022;
acquisition trigger on different events; acquisition triggers at
vsc = 0.8333
rising edge vertical and rising edge horizontal; I-port output
8-bit with SAV/EAV codes like example number 1
4
X-port and H-port for 16-bit Y-C_B-C_R 4 : 2 : 2 input (if no 16-bit 720 × 288 200 × 80 prsc = 2;
output selected); XRH and XRV as references; field detection
fisc = 1.8;
and acquisition trigger at falling edge vertical and rising edge
vsc = 3.6
horizontal; I-port output 8-bit with SAV/EAV codes, but Y only
output
2001 May 30
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