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SAA7118 Datasheet, PDF (121/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input | |||
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Philips Semiconductors
Multistandard video decoder with adaptive
comb ï¬lter and component video input
Preliminary speciï¬cation
SAA7118
15.2.10 SUBADDRESS 09H
Table 47 Luminance control; 09H[7:0]
BIT
D7
DESCRIPTION
chrominance trap/comb ï¬lter
bypass
D6 adaptive luminance comb ï¬lter
D5 processing delay in non comb
ï¬lter mode
D4 remodulation bandwidth for
luminance; see Figs 14 to 17
D[3:0] sharpness control, luminance
ï¬lter characteristic; see Fig.18
SYMBOL VALUE
FUNCTION
BYPS
0 chrominance trap or luminance comb ï¬lter active;
default for CVBS mode
1 chrominance trap or luminance comb ï¬lter bypassed;
default for S-video mode
YCOMB
0 disabled (= chrominance trap enabled, if BYPS = 0)
1 active, if BYPS = 0
LDEL
0 processing delay is equal to internal pipelining delay;
recommended setting
1 one (NTSC standards) or two (PAL standards) video
lines additional processing delay
LUBW
LUFI[3:0]
0
1
0001
small remodulation bandwidth
(narrow chroma notch â higher luminance bandwidth)
large remodulation bandwidth
(wider chroma notch â smaller luminance bandwidth)
resolution enhancement ï¬lter 8.0 dB at 4.1 MHz
0010 resolution enhancement ï¬lter 6.8 dB at 4.1 MHz
0011 resolution enhancement ï¬lter 5.1 dB at 4.1 MHz
0100 resolution enhancement ï¬lter 4.1 dB at 4.1 MHz
0101 resolution enhancement ï¬lter 3.0 dB at 4.1 MHz
0110 resolution enhancement ï¬lter 2.3 dB at 4.1 MHz
0111 resolution enhancement ï¬lter 1.6 dB at 4.1 MHz
0000 plain
1000 low-pass ï¬lter 2 dB at 4.1 MHz
1001 low-pass ï¬lter 3 dB at 4.1 MHz
1010 low-pass ï¬lter 3 dB at 3.3 MHz; 4 dB at 4.1 MHz
1011 low-pass ï¬lter 3 dB at 2.6 MHz; 8 dB at 4.1 MHz
1100 low-pass ï¬lter 3 dB at 2.4 MHz; 14 dB at 4.1 MHz
1101 low-pass ï¬lter 3 dB at 2.2 MHz; notch at 3.4 MHz
1110 low-pass ï¬lter 3 dB at 1.9 MHz; notch at 3.0 MHz
1111 low-pass ï¬lter 3 dB at 1.7 MHz; notch at 2.5 MHz
15.2.11 SUBADDRESS 0AH
Table 48 Luminance brightness control: decoder part; 0AH[7:0]
OFFSET
255 (bright)
128 (ITU level)
0 (dark)
DBRI7
1
1
0
DBRI6
1
0
0
CONTROL BITS D7 TO D0
DBRI5
1
0
0
DBRI4
1
0
0
DBRI3
1
0
0
DBRI2
1
0
0
DBRI1
1
0
0
DBRI0
1
0
0
2001 May 30
121
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