SAA7118 Datasheet, PDF (134/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
15.3 Programming register RGB/Y-P_B-P_R component input processing
15.3.1 SUBADDRESS 23H
Table 67 Analog input control 5 (AICO5); 23H[7:4] and 23H[2:0]
BIT
DESCRIPTION
SYMBOL VALUE
FUNCTION
D7 analog output select
AOSL2
see Table 59
D6 AD port output enable
ADPE
0 AD port is set to 3-state
1 AD port is enabled
D5 ADC clock selector
EXCLK
0 all ADCs are clocked by the internal generated line-locked
clock
1 all ADCs are clocked by the external input clock on CLKEXT
D4 clamping/reference
selection for all ADCs
REFA
0 clamping is dependent on HLNRS[03H[6]]
1 reference selection (input signal is pulled into ADC range)
D2 enable external source
switch indicator input
EXMCLR
EXMCE
0 disabled
1 enabled (any slope on EXMCLR input will reset the internal
gain control loop)
D1 static gain control channel 2 GAI48
sign bit
see Table 69
D0 static gain control channel 1 GAI38
sign bit
see Table 68
15.3.2 SUBADDRESS 24H
Table 68 Analog input control 6 (AICO6): static gain control channel 3; 23H[0] and 24H[7:0]
DECIMAL
VALUE
0...
...144
145...
...511
GAIN
(dB)
−3
0
0
+6
SIGN BIT
23H[0]
GAI38
0
0
0
1
GAI37
0
1
1
1
GAI36
0
0
0
1
CONTROL BITS D7 TO D0
GAI35
0
0
0
1
GAI34
0
1
1
1
GAI33
0
0
0
1
GAI32
0
0
0
1
GAI31
0
0
0
1
GAI30
0
0
1
1
15.3.3 SUBADDRESS 25H
Table 69 Analog input control 7 (AICO7): static gain control channel 4; 23H[1] and 25H[7:0]
DECIMAL
VALUE
0...
...144
145...
...511
GAIN
(dB)
−3
0
0
+6
SIGN BIT
23H[1]
GAI48
0
0
0
1
GAI47
0
1
1
1
GAI46
0
0
0
1
CONTROL BITS D7 TO D0
GAI45
0
0
0
1
GAI44
0
1
1
1
GAI43
0
0
0
1
GAI42
0
0
0
1
GAI41
0
0
0
1
GAI40
0
0
1
1
2001 May 30
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