SAA7118 Datasheet, PDF (88/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ICLK output timing
C_L
output load
capacitance
15
−
50
pF
T_cy
cycle time
δ
duty factors for
t_ICLKH/t_ICLKL
t_r
rise time
0.6 to 2.6 V
t_f
fall time
2.6 to 0.6 V
31
−
45
ns
35
−
65
%
−
−
5
ns
−
−
5
ns
Data and control signal output timing I-port, related to ICLK output (for IPCK[1:0] 87H[5:4] = 00 is default)
C_L
output load
capacitance at all
outputs
15
−
50
pF
t_OHD;DAT
output data hold C_L = 15 pF
time
−
12
−
ns
t_o(d)
output delay time C_L = 15 pF
−
22
−
ns
ICLK input timing
T_cy
cycle time
31
−
100
ns
Notes
1. ADC1 is not taken into account, since component video is always converted by ADC2, ADC3 and ADC4.
2. V_DD(I2C) is the supply voltage of the I²C-bus. For V_DD(I2C) = 3.3 V is V_{IL(SCL,SDA)(max)} = 1 V; for V_DD(I2C) = 5 V is
V_{IL(SCL,SDA)(max)} = 1.5 V. For V_DD(I2C) = 3.3 V is V_{IH(SCL,SDA)(min)} = 2.3 V; for V_DD(I2C) = 5 V is V_{IH(SCL,SDA)(min)} = 3.5 V.
3. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); C_L = 50 pF.
4. The effects of rise and fall times are included in the calculation of t_OHD;DAT and t_PD. Timings and levels refer to
drawings and conditions illustrated in Fig.46.
5. The crystal oscillator drive level is typical 0.28 mW.
2001 May 30
88