SAA7118 Datasheet, PDF (50/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Additionally the bit D7 of SAV and EAV can be defined via CONLH[90H[7]]. CONLH[90H[7]] = 0 (default) sets D7 to logic 1, a logic 1 inverts the
SAV/EAV bit D7. So it is possible to mark the output of the both tasks by different SAV/EAV codes. This bit can also be seen as ‘task flag’ on the
pins IGP0 (IGP1), if TASK output is selected.
Table 10 Examples for field processing
FIELD SEQUENCE FRAME/FIELD
SUBJECT
EXAMPLE 1⁽¹⁾
EXAMPLE 2⁽²⁾⁽³⁾
EXAMPLE 3^(2)(4)(5)
EXAMPLE 4^(2)(4)(6)
1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2
Processed by task
A A ABABABBABBA B BA B BA
State of detected
ITU 656 FID
0 1 00101010101 0 10 1 01
TOGGLE flag
1
0
1
1 1 0 0 1 0 1 1 0 0 0⁽⁷⁾ 1 1 1⁽⁷⁾ 0 0
Bit D6 of SAV/EAV byte
0
1
0
0 1 0 1 1 0 1 1 0 0 0⁽⁷⁾ 1 1 1⁽⁷⁾ 0 0
Required sequence
UP LO UP UP LO UP LO UP LO UP LO UP LO UP LO UP LO UP LO
conversion at the vertical ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
scaler⁽⁸⁾
UP LO UP UP LO UP LO LO UP LO LO UP UP UP LO LO LO UP UP
Output⁽⁹⁾
O O O O O O O O O O O O O NO O O NO O O
Notes
1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0.
2. Tasks are used to scale to different output windows, priority on task B after SWRST.
3. Both tasks at ¹â„₂ frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H.
4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted.
5. Task B at ²â„₃ frame rate constructed from neighbouring motion phases; task A at ¹â„₃ frame rate of equidistant motion phases; OFIDC = 1;
subaddresses 90H at 41H and C0H at 45H.
6. Task A and B at ¹â„₃ frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H.
7. State of prior field.
8. It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines.
9. O = data output; NO = no output.