SAA7118 Datasheet, PDF (56/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
8.4.2.2
Horizontal fine scaling (variable phase delay
filter; subaddresses A8H to AFH and
D8H to DFH)
The horizontal fine scaling (VPD) should operate at scaling
ratios between ¹â„₂ and 2 (0.8 and 1.6), but can also be
used for direct scaling in the range from ¹â„_7.999 to
(theoretical) zoom 3.5 (restriction due to the internal data
path architecture), without prescaler.
In combination with the prescaler a compromise between
sharpness impression and alias can be found, which is a
signal source and application dependent.
For the luminance channel a filter structure with 10 taps is
implemented, and for the chrominance a filter with 4 taps.
Luminance and chrominance scale increments
(XSCY[12:0] A9H[4:0]A8H[7:0] and XSCC[12:0]
ADH[4:0]ACH[7:0]) are defined independently, but must
be set in a 2 : 1 relationship in the actual data path
implementation. The phase offsets XPHY[7:0] AAH[7:0]
and XPHC[7:0] AEH[7:0] can be used to shift the sample
phases slightly. XPHY[7:0] and XPHC[7:0] covers the
phase offset range 7.999T to ¹â„₃₂T. The phase offsets
should also be programmed in a 2 : 1 ratio.
The underlying phase controlling DTO has a 13-bit
resolution.
According to the equations
XSCY[12:0] = 1024 × _{X-----PN----Sp---i-C-x---_[--5-i-n-:--0---]} × _{N-----p---i--x-1--_---o---u----t} and
XSCC[12:0] = ^{X-----S----C----Y--2--[--1---2---:--0---]}
the VPD covers the scale range from 0.125 to zoom 3.5.
VPD acts equivalent to a polyphase filter with 64 possible
phases. In combination with the prescaler, it is possible to
get very accurate samples from a highly anti-aliased
integer downscaled input picture.
8.4.3.1 Line FIFO buffer (subaddresses 91H, B4H and
C1H, E4H)
The line FIFO buffer is a dual ported RAM structure for
768 pixels, with asynchronous write and read access. The
line buffer can be used for various functions, but not all
functions may be available simultaneously.
The line buffer can buffer a complete unscaled active video
line or more than one shorter lines (only for non-mirror
mode), for selective repetition for vertical zoom-up.
For zooming up 240 lines to 288 lines e.g., every fourth
line is requested (read) twice from the vertical scaling
circuitry for calculation.
For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling
scheme (MPEG, video phone, Indeo YUV-9) to ITU like
sampling scheme 4 : 2 : 2, the chrominance line buffer is
read twice or four times, before being refilled again by the
source. It has to be preserved by means of the input
acquisition window definition, so that the processing starts
with a line containing luminance and chrominance
information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits
FSC[2:1] 91H[2:1] define the distance between the Y/C
lines. In the event of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1
have to be set to ‘00’.
The line buffer can also be used for mirroring, i.e. for
flipping the image left to right, for the vanity picture in video
phone applications (bit YMIR[B4H[4]]). In mirror mode only
one active prescaled line can be held in the FIFO at a time.
The line buffer can be utilized as an excessive pipeline
buffer for discontinuous and variable rate transfer
conditions at the expansion port or image port.
8.4.3 VERTICAL SCALING
The vertical scaler of the SAA7118 consists of a line FIFO
buffer for line repetition and the vertical scaler block, which
implements the vertical scaling on the input data stream in
2 different operational modes from theoretical zoom by 64
down to icon size ¹â„₆₄. The vertical scaler is located
between the BCS and horizontal fine scaler, so that the
BCS can be used to compensate the DC gain amplification
of the ACM mode (see Section 8.4.3.2) as the internal
RAMs are only 8-bit wide.
2001 May 30
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