SAA7118 Datasheet, PDF (68/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
8.7.2 SIGNALS ASCLK AND ALRCLK
Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for
channel-select. The frequencies of these signals are defined by the following parameters:
• SDIV[5:0] 38H[5:0] according to the equation:
f_ASCLK = ₍---S----D--f--I^A--V-^M----^X₊---^C--1-^L---^K₎----_×----2-- ⇒ SDIV[5:0] = _2-f-^A--f-^M-_A---^XS---^CC---^L-_L--^KK- – 1
• LRDIV[5:0] 39H[5:0] according to the equation: f_ALRCLK = _L----R--f--^A_D---^S--I-^C_V---^L---^K_×-----2- ⇒ LRDIV[5:0] = _2----ff--^AA---^SL---^CR---^LC--^K-_L---_K-
See Table 23 for examples.
Table 23 Programming examples for ASCLK/ALRCLK clock generation
AMXCLK
(MHz)
12.288
11.2896
8.192
ASCLK
(kHz)
1 536
768
1 411.2
2 822.4
1 024
2 048
SDIV
DECIMAL
3
7
3
1
3
1
HEX
03
07
03
01
03
01
ALRCLK
(kHz)
48
44.1
32
LRDIV
DECIMAL
16
8
16
32
16
32
HEX
10
08
10
10
10
10
8.7.3 OTHER CONTROL SIGNALS
Further control signals are available to define reference clock edges and vertical references:
APLL[3AH[3]]; Audio PLL mode:
0: PLL closed
1: PLL open
AMVR[3AH[2]]; Audio Master clock Vertical Reference:
0: internal V
1: external V
LRPH[3AH[1]]; ALRCLK Phase
0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK
1: don’t invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK
SCPH[3AH[0]]; ASCLK Phase:
0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK
1: don’t invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK.
2001 May 30
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