SAA7118 Datasheet, PDF (76/169 Pages) NXP Semiconductors – Multistandard video decoder with adaptive comb filter and component video input

Philips Semiconductors
Multistandard video decoder with adaptive
comb filter and component video input
Preliminary specification
SAA7118
The following deviations from “ITU 656 recommendation”
are implemented at the SAA7118s image port interface:
• SAV and EAV codes are only present in those lines,
where data is to be transferred, i.e. active video lines, or
VBI raw samples, no codes for empty lines
• There may be more or less than 720 pixels between
SAV and EAV
• Data content and the number of clock cycles during
horizontal and vertical blanking is undefined, and may
not be constant
• Data stream may be interleaved with not-valid data
codes, 00H, but SAV and EAV 4-byte codes are not
interleaved with not-valid data codes
• There may be an irregular pattern of not-valid data, or
IDQ, and as a result, C_B-Y-C_R-Y is not in a fixed phase
to a regular clock divider
• VBI raw sample streams are enveloped with
SAV and EAV, like normal video
• Decoded VBI-data is transported as Ancillary (ANC)
data, two modes:
– direct decoded VBI-data bytes (8-bit) are directly
placed in the ANC data field, 00H and FFH codes
may appear in data block (violation to ITU-R BT.656)
– recoded VBI-data bytes (8-bit) directly placed in ANC
data field, 00H and FFH codes will be recoded to
even parity codes 03H and FCH to suppress invalid
ITU-R BT.656 codes.
There are no empty cycles in the ancillary code and its
data field. The data codes 00H and FFH are suppressed
(changed to 01H or FEH respectively) in the active video
stream, as well as in the VBI raw sample stream (VBI
pass-through). Optionally, the number range can be
further limited.
Table 32 Signals dedicated to the image port
SYMBOL
PIN⁽¹⁾
I/O
DESCRIPTION
BIT
IPD7 to
IPD0
ICLK
IDQ
IGPH
IGPV
IGP1
IGP0
ITRDY
ITRI
K11, J13, J14, I/O I-port data
H13, H14, H11,
G12 and G14
(92 to 94, 97 to
100 and 102)
ICODE[93H[7]], ISWP[1:0]
85H[7:6] and IPE[1:0] 87H[1:0]
M14 (84)
I/O continuous reference clock at image port, can ICKS[1:0] 80H[1:0] and IPE[1:0]
be input or output, as output decoder LLC or 87H[1:0]
XCLK from X-port
L13 (85)
O data valid flag at image port, qualifier, with
programmable polarity;
secondary function: gated clock
ICKS2[80H[2]], IDQP[85H[0]] and
IPE[1:0] 87H[1:0]
K12 (91)
O horizontal reference output signal, copy of the IDH[1:0] 84H[1:0], IRHP[85H[1]]
H-gate signal of the scaler, with programmable and IPE[1:0] 87H[1:0]
polarity; alternative function: HRESET pulse
K14 (90)
O vertical reference output signal, copy of the IDV[1:0] 84H[3:2], IRVP[85H[2]]
V-gate signal of the scaler, with programmable and IPE[1:0] 87H[1:0]
polarity; alternative function: VRESET pulse
K13 (89)
O general purpose output signal for I-port
IDG12[86H[4]], IDG1[1:0] 84H[5:4],
IG1P[85H[3]] and IPE[1:0] 87H[1:0]
L14 (87)
O general purpose output signal for I-port
IDG02[86H[5]], IDG0[1:0] 84H[7:6],
IG0P[85H[4]] and IPE[1:0] 87H[1:0]
N12 (77)
I target ready input signals
−
L12 (86)
I port control, switches I-port into 3-state
IPE[1:0] 87H[1:0]
Note
1. Pin numbers for QFP160 in parenthesis.
2001 May 30
76